100/1000 Tri-Speed Ethernet Phy - Xilinx SP605 Hardware User's Manual

Chapter 1: SP605 Evaluation Board

11. 10/100/1000 Tri-Speed Ethernet PHY

The SP605 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernet
communications at 10, 100, or 1000 Mb/s. The board supports a GMII interface from the
FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through a Halo
HFJ11-1G01E RJ-45 connector with built-in magnetics.
On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY
address 0b00111 using the settings shown in the following table. These settings can be
overwritten via software commands passed over the MDIO interface.
Table 1-14: PHY Configuration Pins
Table 1-15
Table 1-15: Ethernet PHY Connections
34
Connection on
Pin
Board Definition and Value
CFG2 V 2.5V
CC
CFG3 V 2.5V
CC
CFG4 V 2.5V HWCFG_MD[2] = 1
CC
CFG5 V 2.5V
CC
CFG6 PHY_LED_RX
shows the connections and pin numbers for the PHY.
U1 FPGA Pin Schematic Net Name
V20 PHY_MDIO
R19 PHY_MDC
J20 PHY_INT
J22 PHY_RESET
N15 PHY_CRS
M16 PHY_COL
P20 PHY_RXCLK
U20 PHY_RXER
T22 PHY_RXCTL_RXDV
P19 PHY_RXD0
Y22 PHY_RXD1
Y21 PHY_RXD2
W22 PHY_RXD3
W20 PHY_RXD4
V22 PHY_RXD5
V21 PHY_RXD6
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Bit[2] Bit[1]
Definition and Value
ANEG[3] = 1 ANEG[2] = 1
ANEG[0] = 1 ENA_XC = 1
HWCFG_MD[1] = 1
DIS_FC = 1 DIS_SLEEP = 1
SEL_BDT = 0 INT_POL = 1
U46 M88E111
Pin Number
33
35
32
36
115
114
7
8
4
3
128
126
125
124
123
121
Bit[0]
Definition and Value
ANEG[1] = 1
DIS_125 = 1
HWCFG_MD[0] = 1
HWCFG_MD[3] = 1
75/50Ω = 0
Pin Name
MDIO
MDC
INT_B
RESET_B
CRS
COL
RXCLK
RXER
RXDV
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019