Gem3 Ethernet (Mio 64-77); 10/100/1000 Mhz Tri-Speed Ethernet Phy - Xilinx ZCU104 User Manual

GEM3 Ethernet (MIO 64-77)

The PS-side Gigabit Ethernet MAC (GEM) implements a 10/100/1000 Mb/s Ethernet
interface (see Figure
routed to an RJ45 Ethernet connector. The RGMII Ethernet PHY is boot strapped to PHY
address 5'b01100 (0x0C) and Auto Negotiation is set to Enable. The communication with
the device is described in the DP83867 RGMII PHY data sheet
X-Ref Target - Figure 3-9

10/100/1000 MHz Tri-Speed Ethernet PHY

[Figure 2-1, callout 9]
The ZCU104 board uses the TIDP83867IRPAP Ethernet RGMII PHY
Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports RGMII
mode only. The PHY connection to a user-provided Ethernet cable is through a Bel Fuse
L829-1J1T-43 RJ-45 connector (P12) with built-in magnetics and LED indicators. The
connections from XCZU7EV MPSoC U1 to the DP83867IRPAP PHY device U98 (bottom of the
board) are listed in
Table 3-14: DP83867 PHY Connections to XCZU7EV MPSoC
XCZU7EV
(U1) Pin
J31
J32
J34
K28
K29
K30
ZCU104 Board User Guide
UG1267 (v1.1) October 9, 2018
3-9), which connects to a TI DP83867IRPAP Ethernet RGMII PHY U98
RGMII
GEM
MIO
MDIO
Figure 3-9: Ethernet Block Diagram
Table 3-14.
Net Name
MIO64_ENET_TX_CLK
MIO65_ENET_TX_D0
MIO66_ENET_TX_D1
MIO67_ENET_TX_D2
MIO68_ENET_TX_D3
MIO69_ENET_TX_CTRL
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Chapter 3: Board Component Descriptions
[Ref
RJ45 and
TI
Magnetics
DP83867IR
DP83867 PHY U98
Pin #
40
38
37
36
35
52
16].
X16527-100818
[Ref 16] (U98) for
Pin Name
GTX_CLK
TX_DO
TX_D1
TX_D2
TX_D3
TX_EN_TX_CTRL
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