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Detection of pulses
at PLC-inputs
July 2013
The following data apply for single-channel standard PLC inputs and dual-
channel FS inputs of the safe PLC (SPLC).
Minimum required pulse widths in the HSCI system for signal detection by the
control at the standard inputs:
Input
(S)PLC inputs on: X9 of a PLB, PLD in slots 1 to 4,
machine operating panel or UxC 1xx
PLC inputs on PLD in slots 5 to 8
The (S)PLC cycle time must also be observed for actual processing in the
(S)PLC program. The pulse width must be longer than the above mentioned
time + the (S)PLC cycle time in order to ensure that the pulse is processed in
the (S)PLC program.
Minimum required pulse widths in the HSCI system for signal detection by the
control at the special inputs:
Input
Fast PLC inputs on PLD in slots 1 to 4
Emergency stop inputs –ES.A, –ES.B
Pulse widths at (S)PLC inputs that are not detected due to internal hardware
filter run times:
Input
All (S)PLC inputs
Edge low --> high
All (S)PLC inputs
Edge high --> low
Some devices that operate with self-generated test pulses at their input (e.g.
test pulses for wire breakage or cross-circuit detection) should be connected
to machines at the (S)PLC inputs. For example, a low test pulse (high --> low
flank) of such devices must be smaller than 2.0 ms so that they are not
detected due to internal filter run times. If pulses are greater than 2.0 ms it can
cause the control to detect them, forward them to the (S)PLC run-time
environment and trigger the corresponding reactions.
9.1 PLC Functions
Required pulse
width
> 8 ms
> 11 ms
Required pulse
width
> 8 ms
> 5.5 ms
Maximum
Effect
pulse
width
< 0.4 ms
High pulse is not
detected due to
internal filter run times
< 2.0 ms
Low pulse is not
detected due to
internal filter run times
1665
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