Standby Function Operation; Halt Mode - NEC MuPD78F0132H User Manual

19.2 Standby Function Operation

19.2.1 HALT mode

(1) HALT mode
The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU
clock before the setting was the high-speed system clock, Ring-OSC clock, or subsystem clock.
The operating statuses in the HALT mode are shown below.
HALT Mode Setting
Item
System clock
CPU
Port (latch)
16-bit timer/event counter 00
Note 2
16-bit timer/event counter 01
8-bit timer/event counter 50
8-bit timer/event counter 51
8-bit timer H0
8-bit timer H1
Watch timer
Watchdog Ring-OSC cannot
Note 5
timer be stopped
Ring-OSC can be
Note 5
stopped
A/D converter
Serial UART0
interface
UART6
CSI10
Note 2
CSI11
Clock monitor
Multiplier/divider
Power-on-clear function
Low-voltage detection function
External interrupt
Notes 1. When "Stopped by software" is selected for Ring-OSC by the option byte and Ring-OSC is stopped by
software (for option bytes, see CHAPTER 24 OPTION BYTE).
µ
2. PD78F0133H, 78F0134H, 78F0136H, 78F0138H, and 78F0138HD only.
3. Operable when the high-speed system clock is selected.
4. Operation not guaranteed when other than subsystem clock is selected.
5. "Ring-OSC cannot be stopped" or "Ring-OSC can be stopped by software" can be selected by the option
byte.
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CHAPTER 19 STANDBY FUNCTION
Table 19-2. Operating Statuses in HALT Mode (1/2)
When HALT Instruction Is Executed While CPU Is
Operating on High-Speed System Clock
When Ring-OSC When Ring-OSC
Oscillation Continues Oscillation Stopped
When When When
Subsystem Subsystem Subsystem
Clock Used Clock Not Clock Used
Used
Clock supply to the CPU is stopped
Operation stopped
Status before HALT mode was set is retained
Operable
Operable
Operable
Operable
Operable
Operable
Note 3
Operable Operable Operable
Operable
Operation stopped
Operable
Operable
Operable
Operable
Operable
Operable Operation stopped
Operable
Operable
Operable
Operable
User's Manual U16899EJ2V0UD
When HALT Instruction Is Executed While CPU Is
Operating on Ring-OSC Clock
When High-Speed System
Note 1
Clock Oscillation Continues
When When When
Subsystem Subsystem Subsystem
Clock Not Clock Used Clock Not
Used Used
Operation not guaranteed
Operation not guaranteed
Operation not guaranteed when count clock other than
TI50 is selected
Operation not guaranteed when count clock other than
TI51 is selected
Operation not guaranteed when count clock other than
TM50 output is selected during 8-bit timer/event counter
50 operation
Operation not guaranteed when count clock other than
7
f /2 is selected
R
Note 3 Note 4
Operable Operable Operation not
guaranteed
−
Operable
Operation not guaranteed
Operation not guaranteed when serial clock other than
TM50 output is selected during TM50 operation
Operation not guaranteed when serial clock other than
external SCK10 is selected
Operation not guaranteed when serial clock other than
external SCK11 is selected
Operable
Operation not guaranteed
When High-Speed System
Clock Oscillation Stopped
When When
Subsystem Subsystem
Clock Used Clock Not
Used
Note 4
Operable Operation not
guaranteed
Operation stopped