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(8) Timer operation
<1> Even if 16-bit timer counter 0n (TM0n) is read, the value is not captured by 16-bit timer capture/compare
register 01n (CR01n).
<2> Regardless of the CPU's operation mode, when the timer stops, the input signals to the TI00n/TI01n pins
are not acknowledged.
<3> The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
clear & start occurs at the TI00n valid edge. In the mode in which clear & start occurs on a match between
the TM0n register and CR00n register, one-shot pulse output is not possible because an overflow does not
occur.
(9) Capture operation
<1> If the TI00n pin valid edge is specified as the count clock, a capture operation by the capture register
specified as the trigger for the TI00n pin is not possible.
<2> To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles
of the count clock selected by prescaler mode register 0n (PRM0n).
<3> The capture operation is performed at the falling edge of the count clock. An interrupt request input
(INTTM00n/INTTM01n), however, is generated at the rise of the next count clock.
(10) Compare operation
A capture operation may not be performed for CR00n/CR01n set in compare mode even if a capture trigger has
been input.
(11) Edge detection
<1> If the TI00n or TI01n pin is high level immediately after system reset and the rising edge or both the rising
and falling edges are specified as the valid edge of the TI00n or TI01n pin to enable the 16-bit timer counter
0n (TM0n) operation, a rising edge is detected immediately after the operation is enabled. Be careful
therefore when pulling up the TI00n or TI01n pin. However, if the TI00n or TI01n pin is high level when re-
enabling operation after the operation has been stopped, the rising edge is not detected.
<2> The sampling clock used to remove noise differs when the TI00n pin valid edge is used as the count clock
and when it is used as a capture trigger. In the former case, the count clock is f
count clock is selected by prescaler mode register 0n (PRM0n). The capture operation is started only after
a valid edge is detected twice by sampling, thus eliminating noise with a short pulse width.
Remark n = 0:
n = 0, 1:
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
µ
PD78F0132H
µ
PD78F0133H, 78F0134H, 78F0136H, 78F0138H, 78F0138HD
User's Manual U16899EJ2V0UD
, and in the latter case the
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