NEC MuPD78F0132H User Manual page 139

(1) 16-bit timer counter 0n (TM0n)
TM0n is a 16-bit read-only register that counts count pulses.
The counter is incremented in synchronization with the rising edge of the input clock.
Address: FF10H, FF11H (TM00), FFB0H, FFB1H (TM01)
Symbol
TM0n
(n = 0, 1)
The count value is reset to 0000H in the following cases.
<1> At RESET input
<2> If TMC0n3 and TMC0n2 are cleared
<3> If the valid edge of the TI00n pin is input in the mode in which clear & start occurs when inputting the valid
edge of the TI00n pin
<4> If TM0n and CR00n match in the mode in which clear & start occurs on a match of TM0n and CR00n
<5> If OSPT0n is set to 1 in one-shot pulse output mode
(2) 16-bit timer capture/compare register 00n (CR00n)
CR00n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is
used as a capture register or as a compare register is set by bit 0 (CRC0n0) of capture/compare control register
0n (CRC0n).
CR00n can be set by a 16-bit memory manipulation instruction.
RESET input clears this register to 0000H.
Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 00n (CR00n)
Address: FF12H, FF13H (CR000), FFB2H, FFB3H (CR001)
Symbol
CR00n
(n = 0, 1)
• When CR00n is used as a compare register
The value set in CR00n is constantly compared with 16-bit timer counter 0n (TM0n) count value, and an
interrupt request (INTTM00n) is generated if they match. The set value is held until CR00n is rewritten.
• When CR00n is used as a capture register
It is possible to select the valid edge of the TI00n pin or the TI01n pin as the capture trigger. The TI00n or
TI01n pin valid edge is set using prescaler mode register 0n (PRM0n) (see Table 6-2).
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 6-3. Format of 16-Bit Timer Counter 0n (TM0n)
FF11H (TM00)
FFB1H (TM01)
FF13H (CR000)
FFB3H (CR001)
User's Manual U16899EJ2V0UD
After reset: 0000H R
FF10H (TM00)
FFB0H (TM01)
After reset: 0000H R/W
FF12H (CR000)
FFB2H (CR001)
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