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10.3 Registers Controlling Watchdog Timer
The watchdog timer is controlled by the following two registers.
• Watchdog timer mode register (WDTM)
• Watchdog timer enable register (WDTE)
(1) Watchdog timer mode register (WDTM)
This register sets the overflow time and operation clock of the watchdog timer.
This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be
written only once after reset is released.
RESET input sets this register to 67H.
Figure 10-2. Format of Watchdog Timer Mode Register (WDTM)
Address: FF98H
After reset: 67H
7
Symbol
0
WDTM
Note 1
WDCS4
WDCS3
0
0
1
Note 2
WDCS2
WDCS1
0
0
0
0
1
1
1
1
Notes 1.
If "Ring-OSC cannot be stopped" is specified by the option byte, this cannot be set. The Ring-
OSC clock will be selected no matter what value is written.
2.
Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
234
CHAPTER 10 WATCHDOG TIMER
R/W
6
5
4
1
1
WDCS4
Note 1
0
Ring-OSC clock (f
)
R
1
High-speed system clock (f
×
Watchdog timer operation stopped
Note 2
Note 2
WDCS0
During Ring-OSC clock
11
0
0
2
/f
(4.27 ms)
R
12
0
1
2
/f
(8.53 ms)
R
13
1
0
2
/f
(17.07 ms)
R
14
1
1
2
/f
(34.13 ms)
R
15
0
0
2
/f
(68.27 ms)
R
16
0
1
2
/f
(136.53 ms)
R
17
1
0
2
/f
(273.07 ms)
R
18
1
1
2
/f
(546.13 ms)
R
User's Manual U16899EJ2V0UD
3
2
WDCS3
WDCS2
Operation clock selection
)
XP
Overflow time setting
During high-speed system clock
operation
13
2
/f
(819.2
XP
14
2
/f
(1.64 ms)
XP
15
2
/f
(3.28 ms)
XP
16
2
/f
(6.55 ms)
XP
17
2
/f
(13.11 ms)
XP
18
2
/f
(26.21 ms)
XP
19
2
/f
(52.43 ms)
XP
20
2
/f
(104.86 ms)
XP
1
0
WDCS1
WDCS0
operation
µ
s)
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