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(7) Clock monitor status after Ring-OSC clock oscillation is stopped by software
CPU operation
High-speed system clock
Ring-OSC clock
Note
RSTOP
CLME
Clock monitor status
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before or while oscillation of the Ring-OSC
clock is stopped, monitoring automatically starts after the Ring-OSC clock is stopped. Monitoring is stopped when
oscillation of the Ring-OSC clock is stopped.
Note If it is specified by the option byte that Ring-OSC cannot be stopped, the setting of bit 0 (RSTOP) of the
Ring-OSC mode register (RCM) is invalid. To set RSTOP, be sure to confirm that bit 1 (MCS) of the main
clock mode register (MCM) is 1.
CHAPTER 21 CLOCK MONITOR
Figure 21-3. Timing of Clock Monitor (4/4)
Normal operation (high-speed system clock or subsystem clock)
Oscillation stopped
Monitoring
Monitoring
stopped
User's Manual U16899EJ2V0UD
Monitoring
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