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25.3 Register Controlling ROM Correction
The ROM correction is controlled by the correction control register (CORCN).
(1) Correction control register (CORCN)
This register controls whether or not the correction branch request signal is generated when the fetch address
matches the correction address set in correction address registers 0 and 1. The correction control register
consists of correction enable flags (COREN0, COREN1) and correction status flags (CORST0, CORST1). The
correction enable flags enable or disable the comparator match detection signal, and correction status flags
show the values are matched.
CORCN is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CORCN to 00H.
Clear CORST0 and CORST1 using software.
Symbol
7
6
5
CORCN
0
0
0
Note Do not set bits 0 and 2 to 1.
CHAPTER 25 ROM CORRECTION
Figure 25-3. Format of Correction Control Register
4
<3>
<2>
<1>
<0>
0
COREN1 CORST1 COREN0 CORST0
User's Manual U16899EJ2V0UD
Address
After reset
00H
FF8AH
CORST0
Correction Address Register 0 and Fetch Address Match Detection
0
Not detected
1
Detected
COREN0
Correction Address Register 0 and Fetch Address
Match Detection Control
0
Disabled
1
Enabled
CORST1
Correction Address Register 1 and Fetch Address Match Detection
Not detected
0
Detected
1
COREN1
Correction Address Register 1 and Fetch Address
Match Detection Control
Disabled
0
Enabled
1
R/W
Note
R/W
421
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