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(4) When CPU clock and watchdog timer operation clock are the Ring-OSC clocks (f
instruction execution
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0 but holds its value.
Figure 10-7. Operation in STOP Mode (CPU Clock and WDT Operation Clock: Ring-OSC Clock)
Normal operation
(Ring-OSC clock)
CPU operation
f
XP
f
R
Watchdog timer
Operating Operation stopped
10.4.4 Watchdog timer operation in HALT mode (when "Ring-OSC can be stopped by software" is selected by
option byte)
The watchdog timer stops counting during HALT instruction execution regardless of whether the CPU clock is the
high-speed system clock (f
watchdog timer is the high-speed system clock (f
started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0
but holds its value.
Normal operation
CPU operation
f
XP
f
R
f
XT
Watchdog timer
Operating
CHAPTER 10 WATCHDOG TIMER
STOP
Clock supply stopped
Oscillation
Oscillation stabilization time
stopped
), Ring-OSC clock (f
), or subsystem clock (f
XP
R
) or Ring-OSC clock (f
XP
Figure 10-8. Operation in HALT Mode
HALT
Operation stopped
User's Manual U16899EJ2V0UD
Normal operation (Ring-OSC clock)
(set by OSTS register)
17 clocks
Operating
), or whether the operation clock of the
XT
). After HALT mode is released, counting is
R
Normal operation
Operating
) during STOP
R
241
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