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E.1 Major Revisions in This Edition
Page
p. 18
Addition of
Information
p. 22
Modification of 1.5 Kx1 Series Lineup
p. 42
Modification of recommended connection for unused RESET pin in Table 2-2 Pin I/O Circuit Types
p. 117
Addition of Cautions 1 and 2 to Figure 5-7 Format of Oscillation Stabilization Time Select Register
(OSTS)
p. 116 in previous
Deletion of (7) System wait control register (VSWC) in 5.3 Registers Controlling Clock Generator
edition
p. 143
Addition of description for when used as capture register to Interrupt request generation column in Figure 6-6
Format of 16-Bit Timer Mode Control Register 00 (TMC00)
p. 144
Addition of description for when used as capture register to Interrupt request generation column in Figure 6-7
Format of 16-Bit Timer Mode Control Register 01 (TMC01)
Modification of Note 1 and correction of Cautions 4 and 5 in Figure 6-12 Format of Prescaler Mode
p. 150
Register 00 (PRM00)
p. 152
Modification of Note 1 and correction of Cautions 4 and 5 in Figure 6-13 Format of Prescaler Mode
Register 01 (PRM01)
p. 184
Modification of Note in Figure 7-5 Format of Timer Clock Selection Register 50 (TCL50)
p. 185
Modification of Note in Figure 7-6 Format of Timer Clock Selection Register 51 (TCL51)
p. 203
Modification of Note 1 in Figure 8-5 Format of 8-Bit Timer H Mode Register 0 (TMHMD0)
p. 205
Modification of Note in Figure 8-6 Format of 8-Bit Timer H Mode Register 1 (TMHMD1)
p. 231
Correction of Table 10-1 Loop Detection Time of Watchdog Timer
p. 244
Addition of Note to Figure 11-2 Format of Clock Output Selection Register (CKS)
p. 274
Modification of Note 1 in Figure 13-4 Format of Baud Rate Generator Control Register 0 (BRGC0)
p. 299
Modification of Note 1 in Figure 14-8 Format of Clock Selection Register 6 (CKSR6)
p. 317
Modification of (h) SBF transmission in 14.4.2 Asynchronous serial interface (UART) mode
p. 331
Modification of Note in Figure 15-5 Format of Serial Clock Selection Register 10 (CSIC10)
p. 333
Modification of Note in Figure 15-6 Format of Serial Clock Selection Register 11 (CSIC11)
p. 362
Modification of Caution 3 in Figure 17-2 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L,
IF1H)
p. 379
Addition of Cautions 1 and 2 to Figure 19-2 Format of Oscillation Stabilization Time Select Register
(OSTS)
p. 390
Modification of Figure 20-1 Block Diagram of Reset Function
p. 410
Modification of Note in Figure 23-3 Format of Low-Voltage Detection Level Selection Register (LVIS)
p. 439
Modification of Figure 26-11 FLMD1 Pin Connection Example
p. 442
Addition of description to 26.6.7 Power supply
p. 473
Revision of CHAPTER 29 ELECTRICAL SPECIFICATIONS from target specifications to official
specifications
Addition of package drawings of 64-pin plastic FBGA (6 × 6) and 64-pin plastic LQFP (12 × 12) to CHAPTER
pp. 492, 493
30 PACKAGE DRAWINGS
p. 494
Addition of CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS
p. 498
Revision of APPENDIX A DEVELOPMENT TOOLS
APPENDIX E REVISION HISTORY
µ
PD78F0138HF1-BA2, 78F0138HDGK-8A8, and 78F0138HDF1-BA2 to 1.3 Ordering
User's Manual U16899EJ2V0UD
Description
(1/2)
539
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