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Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the
Ring-OSC clock, the operation of 16-bit timer/event counter 00 is not guaranteed. When an
external clock is used and when the Ring-OSC clock is selected and supplied to the CPU, the
operation of 16-bit timer/event counter 00 is not guaranteed, either, because the Ring-OSC
clock is supplied as the sampling clock to eliminate noise.
2. Always set data to PRM00 after stopping the timer operation.
3. If the valid edge of the TI000 pin is to be set for the count clock, do not set the clear & start
mode using the valid edge of the TI000 pin and the capture trigger.
4. If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is
immediately detected after the rising edge or both the rising and falling edges are set as the
valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00
(TM00). Care is therefore required when pulling up the TI000 or TI010 pin. However, if the
TI000 or TI010 pin is high level when re-enabling operation after the operation has been
stopped, the rising edge is not detected.
5. When the valid edge of the TI010 pin is used, P01 cannot be used as the timer output pin
(TO00). When P01 is used as the TO00 pin, the valid edge of the TI010 pin cannot be used.
Remarks 1. f
: High-speed system clock oscillation frequency
X
2. Figures in parentheses are for operation with f
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User's Manual U16899EJ2V0UD
= 10 MHz.
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