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Figure 6-9. Format of Capture/Compare Control Register 01 (CRC01)
Address: FFB8H
After reset: 00H
Symbol
7
CRC01
0
CRC012
0
1
CRC011
0
1
CRC010
0
1
Note The capture operation is not performed if both the rising and falling edges are specified as the valid edge of
the TI001 pin.
Cautions 1. Timer operation must be stopped before setting CRC01.
2. When the mode in which clear & start occurs on a match between TM01 and CR001 is
selected with 16-bit timer mode control register 01 (TMC01), CR001 should not be specified
as a capture register.
3. To ensure that the capture operation is performed properly, the capture trigger requires a
pulse longer than two cycles of the count clock selected by prescaler mode register 01
(PRM01).
(3) 16-bit timer output control register 0n (TOC0n)
This register controls the operation of the 16-bit timer/event counter 0n output controller. It sets/resets the timer
output F/F (LV0n), enables/disables output inversion and 16-bit timer/event counter 0n timer output,
enables/disables the one-shot pulse output operation, and sets the one-shot pulse output trigger via software.
TOC0n can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TOC0n to 00H.
µ
Remark n = 0:
PD78F0132H
µ
n = 0, 1:
PD78F0133H, 78F0134H, 78F0136H, 78F0138H, 78F0138HD
146
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
R/W
6
5
0
0
CR011 operating mode selection
Operates as compare register
Operates as capture register
Captures on valid edge of TI011 pin
Captures on valid edge of TI001 pin by reverse phase
CR001 operating mode selection
Operates as compare register
Operates as capture register
User's Manual U16899EJ2V0UD
4
3
2
0
0
CRC012
CR001 capture trigger selection
Note
1
0
CRC011
CRC010
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