Registers Controlling Low-Voltage Detector - NEC MuPD78F0132H User Manual

23.3 Registers Controlling Low-Voltage Detector

The low-voltage detector is controlled by the following registers.
• Low-voltage detection register (LVIM)
• Low-voltage detection level selection register (LVIS)
(1) Low-voltage detection register (LVIM)
This register sets low-voltage detection and the operation mode.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears LVIM to 00H.
Figure 23-2. Format of Low-Voltage Detection Register (LVIM)
Address: FFBEH After reset: 00H
<7>
Symbol
LVION
LVIM
Notes 3, 4
LVION
0 Disables operation
1 Enables operation
Note 3
LVIMD
0 Generates interrupt signal when supply voltage (V
1 Generates internal reset signal when supply voltage (V
Note 5
LVIF
0 Supply voltage (V
1 Supply voltage (V
Notes 1. Bit 0 is read-only.
2. Bit 4 may be 0 or 1. This bit corresponds to the LVIE bit in the 78K0/KE1.
3. LVION and LVIMD are cleared to 0 in the case of a reset other than an LVI reset. These are
not cleared to 0 in the case of an LVI reset.
4. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use
software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is
confirmed at LVIF.
5. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and
LVIMD = 0.
Caution To stop LVI, follow either of the procedures below.
• When using 8-bit manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
CHAPTER 23 LOW-VOLTAGE DETECTOR
Note 1
R/W
6 5 4
Note 2
0 0 0
Enables low-voltage detection operation
Low-voltage detection operation mode selection
Low-voltage detection flag
) ≥ detection voltage (V
DD
) < detection voltage (V
DD
User's Manual U16899EJ2V0UD
3 2 <1>
0 0 LVIMD
) < detection voltage (V
DD
) < detection voltage (V
DD
), or when operation is disabled
LVI
)
LVI
<0>
LVIF
)
LVI
)
LVI
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