Peripheral Hardware That Generates Wait - NEC MuPD78F0132H User Manual

32.2 Peripheral Hardware That Generates Wait

Table 32-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait
clocks.
Table 32-1. Registers That Generate Wait and Number of CPU Wait Clocks
Peripheral Hardware
Watchdog timer
Serial interface UART0
Serial interface UART6
A/D converter
Note No wait cycle is generated for the CPU if the number of wait clocks calculated by the above expression is 1.
Caution When the CPU is operating on the subsystem clock and the high-speed system clock is stopped
(MCC = 1), do not access the registers listed above using an access method in which a wait request
is issued.
Remark The clock is the CPU clock (f
496
CHAPTER 32 CAUTIONS FOR WAIT
Register
WDTM Write
ASIS0 Read
ASIS6 Read
ADM Write
ADS Write
PFM Write
PFT Write
ADCR Read
<Calculating maximum number of wait clocks>
) × 2/(1/f
{(1/f )} + 1
MACRO CPU
*The result after the decimal point is truncated if it is less than t
(1/f ), and is rounded up if it exceeds t
CPU
f : Macro operating frequency
MACRO
(When bit 5 (FR2) of ADM = "1": f
f : CPU clock frequency
CPU
t : Low-level width of CPU clock
CPUL
).
CPU
User's Manual U16899EJ2V0UD
Access Number of Wait Clocks
3 clocks (fixed)
1 clock (fixed)
1 clock (fixed)
2 to 5 clocks
(when ADM.5 flag = "1")
2 to 9 clocks
(when ADM.5 flag = "0")
1 to 5 clocks
(when ADM.5 flag = "1")
1 to 9 clocks
(when ADM.5 flag = "0")
after it has been multiplied by
CPUL
.
CPUL
/2, when bit 5 (FR2) of ADM = "0": f
X
Note
Note
2
/2 )
X