NEC MuPD78F0132H User Manual page 236

The relationship between the watchdog timer operation and the internal reset signal generated by the watchdog
timer is shown below.
Table 10-4. Relationship Between Watchdog Timer Operation and
Watchdog Timer
"Ring-OSC Cannot Be
Operation
Stopped by Software" Is
Selected by Option Byte
Internal
(Watchdog Timer Is
Reset Signal
Generation Cause
Watchdog timer Internal reset signal is
overflows generated.
Write to WDTM for the Internal reset signal is
second time generated.
Write other than "ACH" Internal reset signal is
to WDTE generated.
Access WDTE by 1-bit
memory manipulation
instruction
236
CHAPTER 10 WATCHDOG TIMER
Internal Reset Signal Generated by Watchdog Timer
"Ring-OSC Can Be Stopped by Software" Is Selected by Option Byte
Watchdog Timer Is
Always Operating)
Internal reset signal is
generated.
Internal reset signal is
generated.
Internal reset signal is
generated.
User's Manual U16899EJ2V0UD
Operating
WDCS4 Is Set to 1
Internal reset signal is
not generated and the
watchdog timer does
not resume operation.
Internal reset signal is
not generated.
Watchdog Timer Stopped
Source Clock to
Watchdog Timer Is
Stopped
− −
Internal reset signal is
generated when the
source clock to the
watchdog timer
resumes operation.
Internal reset signal is
generated when the
source clock to the
watchdog timer
resumes operation.