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10.1 Functions of Watchdog Timer
The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset
signal is generated.
When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1.
For details of RESF, refer to CHAPTER 20 RESET FUNCTION.
During Ring-OSC Clock Operation
11
2
/f
(4.27 ms)
R
12
2
/f
(8.53 ms)
R
13
2
/f
(17.07 ms)
R
14
2
/f
(34.13 ms)
R
15
2
/f
(68.27 ms)
R
16
2
/f
(136.53 ms)
R
17
2
/f
(273.07 ms)
R
18
2
/f
(546.13 ms)
R
Remarks 1. f
The operation mode of the watchdog timer (WDT) is switched according to the option byte setting of the on-chip
Ring-OSC as shown in Table 10-2.
CHAPTER 10 WATCHDOG TIMER
Table 10-1. Loop Detection Time of Watchdog Timer
Loop Detection Time
: Ring-OSC clock oscillation frequency
R
2. f
: High-speed system clock oscillation frequency
XP
3. Figures in parentheses apply to operation at f
User's Manual U16899EJ2V0UD
During High-Speed System Clock Operation
µ
13
2
/f
(819.2
s)
XP
14
2
/f
(1.64 ms)
XP
15
2
/f
(3.28 ms)
XP
16
2
/f
(6.55 ms)
XP
17
2
/f
(13.11 ms)
XP
18
2
/f
(26.21 ms)
XP
19
2
/f
(52.43 ms)
XP
20
2
/f
(104.86 ms)
XP
= 480 kHz (MAX.), f
R
= 10 MHz
XP
231
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