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(2) Port registers (P0 to P7, P12 to P14)
These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output
latch is read.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H (but P2 is undefined).
Symbol
7
6
P0
0
P06
7
6
P1
P17
P16
7
6
P2
P27
P26
7
6
P3
0
0
7
6
P4
0
0
7
6
P5
0
0
7
6
P6
0
0
7
6
P7
P77
P76
7
6
P12
0
0
7
6
P13
0
0
7
6
P14
0
0
Pmn
0
Output 0
1
Output 1
106
CHAPTER 4 PORT FUNCTIONS
Figure 4-22. Format of Port Register
5
4
3
P05
P04
P03
5
4
3
P15
P14
P13
5
4
3
P25
P24
P23
5
4
3
0
0
P33
5
4
3
0
0
P43
5
4
3
0
0
P53
5
4
3
0
0
P63
5
4
3
P75
P74
P73
5
4
3
0
0
0
5
4
3
0
0
0
5
4
3
0
0
0
Output data control (in output mode)
User's Manual U16899EJ2V0UD
2
1
0
P02
P01
P00
2
1
0
P12
P11
P10
2
1
0
P22
P21
P20
2
1
0
P32
P31
P30
2
1
0
P42
P41
P40
2
1
0
P52
P51
P50
2
1
0
P62
P61
P60
2
1
0
P72
P71
P70
2
1
0
0
0
P120
2
1
0
0
0
P130
2
1
0
0
P141
P140
m = 0 to 7, 12 to 14; n = 0 to 7
Input data read (in input mode)
Input low level
Input high level
Address
After reset
FF00H
00H (output latch)
FF01H
00H (output latch)
FF02H
Undefined
FF03H
00H (output latch)
FF04H
00H (output latch)
FF05H
00H (output latch)
FF06H
00H (output latch)
FF07H
00H (output latch)
FF0CH
00H (output latch)
FF0DH
00H (output latch)
FF0EH
00H (output latch)
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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