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22.4 Cautions for Power-on-Clear Circuit
In a system where the supply voltage (V
voltage (V
), the system may be repeatedly reset and released from the reset status. In this case, the time from
POC
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
Figure 22-3. Example of Software Processing After Release of Reset (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
Checking cause
(set to 50 ms)
Check stabilization
Note 1
Change CPU clock
No
50 ms has passed?
(TMIFH1 = 1?)
Notes 1.
If reset is generated again during this period, initialization processing is not started.
2.
A flowchart is shown on the next page.
406
CHAPTER 22 POWER-ON-CLEAR CIRCUIT
) fluctuates for a certain period in the vicinity of the POC detection
DD
; The
Reset
;
The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
Note 2
of reset
can be identified by the RESF register.
Power-on-clear
;
8-bit timer H1 can operate with the Ring-OSC clock.
Start timer
Source: f
(f
R
;
Check the stabilization of oscillation of the high-speed system
of oscillation
clock by using the OSTC register.
;
Change the CPU clock from the Ring-OSC clock to the high-speed
system clock.
;
TMIFH1 = 1: Interrupt request is generated.
Yes
Initialization
;
Initialization of ports
processing
User's Manual U16899EJ2V0UD
Ring-OSC clock is set as the CPU clock when the reset signal is generated
× compare value 200 = 53 ms
7
(480 kHz (MAX.))/2
R
: Ring-OSC clock oscillation frequency)
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