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Interrupt
Default
Note 1
Type
Priority
Maskable
24
INTDMU
25
INTCSI11
26
INTTM001
27
INTTM011
−
Software
BRK
−
Reset
RESET
POC
LVI
Clock monitor High-speed system clock oscillation stop
WDT
Notes 1.
The default priority is the priority applicable when two or more maskable interrupt are generated
simultaneously. 0 is the highest priority, and 27 is the lowest.
2.
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 17-1.
3.
The interrupt sources INTCSI11, INTTM001, and INTTM011 are available only in the
78F0134H, 78F0136H, 78F0138H, and 78F0138HD.
4.
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 1.
CHAPTER 17 INTERRUPT FUNCTIONS
Table 17-1. Interrupt Source List (2/2)
Interrupt Source
Name
End of multiply/divide operation
Note 3
End of CSI11 communication
Note 3
Match between TM01 and CR001 (when
compare register is specified), TI011 pin valid
edge detection (when capture register is
specified)
Note 3
Match between TM01 and CR011 (when
compare register is specified), TI001 pin valid
edge detection (when capture register is
specified)
BRK instruction execution
Reset input
Power-on clear
Low-voltage detection
detection
WDT overflow
User's Manual U16899EJ2V0UD
Internal/
External
Trigger
Internal
Note 4
Vector
Basic
Table
Configuration
Note 2
Address
Type
0034H
(A)
0036H
0038H
003AH
−
003EH
(D)
−
−
0000H
µ
PD78F0133H,
357
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