NEC MuPD754202 Datasheet

Mos integrated circuit, 4-bit single-chip microcontrollers

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The µ PD754202 is a member of the 75XL Series of 4-bit single-chip microcontrollers that enable data processing
equivalent to that of an 8-bit microcontroller.
It features expanded CPU functions compared to the 75X Series and enables high-speed, low-voltage operation
at 1.8 V, making it suitable for battery-driven applications.
The µ PD754202(A) is a higher-reliability product compared to the µ PD754202.
Detailed function descriptions, etc., are provided in the following user's manual. Be sure to read it
when designing.
FEATURES
Key return reset function for keyless entry
Low-voltage operation: V
On-chip memory
• Program memory (ROM): 2048 × 8 bits
• Data memory (RAM)
Variable instruction execution time useful for high-speed operation and power save
• 0.95, 1.91, 3.81, 15.3 µ s (at 4.19-MHz operation)
• 0.67, 1.33, 2.67, 10.7 µ s (at 6.0-MHz operation)
Compact package (20-pin plastic shrink SOP (300 mil, 0.65-mm pitch))
APPLICATIONS
Automotive electronics such as keyless entry units
The µ PD754202 and µ PD754202(A) have different quality grades. Unless otherwise specified, descriptions in
this data sheet apply to the µ PD754202.
Document No. U12181EJ1V0DS00 (1st edition)
Date Published May 1997 N
Printed in Japan
DATA SHEET
µ PD754202, 754202(A)
4-BIT SINGLE-CHIP MICROCONTROLLERS
µ PD754202 User's Manual: U11132E
= 1.8 to 6.0 V
DD
: 128 × 4 bits
The information in this document is subject to change without notice.
MOS INTEGRATED CIRCUIT
©
1997

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Summary of Contents for NEC MuPD754202

  • Page 1 DATA SHEET MOS INTEGRATED CIRCUIT µ PD754202, 754202(A) 4-BIT SINGLE-CHIP MICROCONTROLLERS The µ PD754202 is a member of the 75XL Series of 4-bit single-chip microcontrollers that enable data processing equivalent to that of an 8-bit microcontroller. It features expanded CPU functions compared to the 75X Series and enables high-speed, low-voltage operation at 1.8 V, making it suitable for battery-driven applications.
  • Page 2 Remark ××× indicates the ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Differences between µ PD754202 and µ PD754202(A) Part Number µ...
  • Page 3 µ PD754202, 754202(A) FUNCTION LIST Parameter Function • 0.95, 1.91, 3.81, 15.3 µ s (system clock: at 4.19-MHz operation) Instruction execution time • 0.67, 1.33, 2.67, 10.7 µ s (system clock: at 6.0-MHz operation) 2048 × 8 bits On-chip memory 128 ×...
  • Page 4: Table Of Contents

    µ PD754202, 754202(A) CONTENTS 1. PIN CONFIGURATION (Top View) ....................6 2. BLOCK DIAGRAM ..........................7 3. PIN FUNCTION ............................ 8 3.1 Port Pins ............................8 3.2 Non-port Pins ..........................9 3.3 Pin Input/Output Circuits ......................10 3.4 Recommended Connection of Unused Pins ................11 4.
  • Page 5 µ PD754202, 754202(A) APPENDIX A. µ PD754202, 75F4264 FUNCTION LIST ..............58 APPENDIX B. DEVELOPMENT TOOLS ....................59 APPENDIX C. RELATED DOCUMENTS ....................62...
  • Page 6: Pin Configuration (Top View)

    µ PD754202, 754202(A) 1. PIN CONFIGURATION (Top View) • 20-pin plastic SOP (300 mil, 1.27-mm pitch) µ PD754202GS-×××-BA5 µ PD754202GS(A)-×××-BA5 • 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) µ PD754202GS-×××-GJG µ PD754202GS(A)-×××-GJG RESET KRREN P30/PTO0 P31/PTO1 P32/PTO2 P70/KR4 P61/INT0 P71/KR5 P72/KR6 P73/KR7...
  • Page 7: Block Diagram

    µ PD754202, 754202(A) BLOCK DIAGRAM BASIC INTERVAL PORT3 P30-P33 TIMER/WATCHDOG TIMER SP (8) INTBT RESET PORT6 P60-P63 8-BIT TIMER PTO0/P30 COUNTER#0 INTT0 TOUT PROGRAM COUNTER INTT1 BANK PORT7 P70-P73 8-BIT PTO1/P31 TIMER GENERAL REG. COUNTER#1 CASCADED 16-BIT TIMER PROGRAM MEMORY PORT8 DATA MEMORY 8-BIT...
  • Page 8: Pin Function

    µ PD754202, 754202(A) PIN FUNCTION 3.1 Port Pins Alternate 8-bit I/O Circuit Pin Name Input/Output Function After Reset Function Type Note Programmable 4-bit input/output port Input/Output PTO0 – Input (PORT3). PTO1 This port can be specified input/output bit- wise. PTO2 On-chip pull-up resistor can be specified by –...
  • Page 9: Non-Port Pins

    µ PD754202, 754202(A) 3.2 Non-port Pins Alternate I/O Circuit Pin Name Input/Output Function After Reset Note Function Type PTO0 Output Timer counter output Input PTO1 PTO2 INT0 Input Edge detection vectored Noise eliminator/ Input F -A interrupt input (detected asynchronous edge is selectable) selectable Noise eliminator...
  • Page 10: Pin Input/Output Circuits

    µ PD754202, 754202(A) 3.3 Pin Input/Output Circuits The µ PD754202 pin input/output circuits are shown schematically. TYPE A TYPE D data P-ch P-ch N-ch output N-ch disable Push-pull output that can be placed in output CMOS standard input buffer high-impedance (both P-ch and N-ch off). TYPE B TYPE E-B P.U.R.
  • Page 11: Recommended Connection Of Unused Pins

    µ PD754202, 754202(A) 3.4 Recommended Connection of Unused Pins Table 3-1. List of Recommended Connection of Unused Pins Recommended Connecting Method P30/PTO0 Input state : Independently connect to V or V via a resistor. P31/PTO1 Output state: Leave open. P32/PTO2 P61/INT0 P70/KR4 Connect to V...
  • Page 12: Switching Function Between Mk I Mode And Mk Ii Mode

    µ PD754202, 754202(A) SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Differences between Mk I Mode and Mk II Mode The µ PD754202 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by bit 3 of the stack bank select register (SBS).
  • Page 13: Setting Method Of Stack Bank Select Register (Sbs)

    µ PD754202, 754202(A) 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program.
  • Page 14: Memory Configuration

    µ PD754202, 754202(A) MEMORY CONFIGURATION Program Memory (ROM): 2048 × 8 bits (0000H-07FFH) • • Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written.
  • Page 15 µ PD754202, 754202(A) Figure 5-1. Program Memory Map Address 0000H MBE RBE Internal reset start address (high-order 3 bits) 0001H Internal reset start address (low-order 8 bits) MBE RBE INTBT start address (high-order 3 bits) 0002H CALLF !faddr instruction entry address INTBT start address (low-order 8 bits) 0003H...
  • Page 16 µ PD754202, 754202(A) Figure 5-2. Data Memory Map Data memory Memory bank 000H General-purpose (32 × 4) register area 01FH 020H Data area Stack area static RAM (128 × 4) 128 × 4 (96 × 4) 07FH 080H 0FFH Not incorporated F80H 128 ×...
  • Page 17: Peripheral Hardware Function

    µ PD754202, 754202(A) PERIPHERAL HARDWARE FUNCTION 6.1 Digital I/O Port The following two types of I/O ports are provided. • CMOS Input (PORT7) • CMOS Input/Output (PORT3, 6, 8) : Total Table 6-1. Types and Features of Digital Ports Port Name Function Operation and Features Remarks...
  • Page 18 µ PD754202, 754202(A) Figure 6-1. Clock Generator Block Diagram · Basic interval timer (BT) · Timer counter · INT0 noise eliminator 1/1 to 1/4096 System clock Divider oscillator 1/2 1/41/16 Oscillation stops Divider Φ · CPU · INT0 noise eliminator PCC0 PCC1 HALT F/F...
  • Page 19: Basic Interval Timer/Watchdog Timer

    µ PD754202, 754202(A) 6.3 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. (a) Interval timer operation to generate a reference time interrupt (b) Watchdog timer operation to detect a runaway of program and reset the CPU (c) Selects and counts the wait time when the standby mode is released (d) Reads the contents of counting Figure 6-2.
  • Page 20: Timer Counter

    µ PD754202, 754202(A) 6.4 Timer Counter The µ PD754202 incorporates three timer counters. Its configuration is shown in Figures 6-3, 6-4, and 6-5. The timer counter functions are shown below. (a) Programmable interval timer operation (b) Square wave output of any frequency to PTO0-PTO2 pins (c) Count value read function The timer counter can operate in the following four modes as set by the mode register.
  • Page 21 µ PD754202, 754202(A)
  • Page 22 µ PD754202, 754202(A)
  • Page 23 µ PD754202, 754202(A)
  • Page 24: Bit Sequential Buffer

    µ PD754202, 754202(A) 6.5 Bit Sequential Buffer ..16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing large data bit-wise.
  • Page 25: Interrupt Function And Test Function

    µ PD754202, 754202(A) INTERRUPT FUNCTION AND TEST FUNCTION The µ PD754202 is provided with five types of interrupt sources and one test source to enable a variety of applications. The interrupt control circuit of the µ PD754202 has the following functions. (1) Interrupt function •...
  • Page 26 µ PD754202, 754202(A)
  • Page 27: Standby Function

    µ PD754202, 754202(A) STANDBY FUNCTION In order to reduce power dissipation while a program is in standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the µ PD754202. Table 8-1. Operation Status in Standby Mode Mode STOP mode HALT mode...
  • Page 28: Reset Function

    µ PD754202, 754202(A) RESET FUNCTION 9.1 Configuration and Operation Status of Reset Function There are three kinds of reset input: the external reset signal (RESET), the reset signal sent from the basic interval/watchdog timer, and the reset signal generated by a falling edge signal from KRn in the STOP mode. When any of these reset signals is input, an internal reset signal is generated.
  • Page 29 µ PD754202, 754202(A) The RESET signal generation initializes each hardware as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation Note Wait RESET signal generated Operation mode or standby mode HALT mode Operation mode...
  • Page 30 µ PD754202, 754202(A) Table 9-1. Hardware Status After Reset (1/3) RESET signal generation RESET signal generation Hardware in the standby mode in operation Program counter (PC) Sets the low-order 3 bits of Sets the low-order 3 bits of program memory’s address program memory’s address 0000H to the PC10-PC8 and the 0000H to the PC10-PC8 and the...
  • Page 31 µ PD754202, 754202(A) Table 9-1. Hardware Status After Reset (2/3) RESET signal generation RESET signal generation Hardware in the standby mode in operation Clock generator Processor clock control register (PCC) Interrupt Interrupt request flag (IRQ×××) Reset (0) Reset (0) function Interrupt enable flag (IE×××) Interrupt master enable flag (IME) Interrupt priority selection register (IPS)
  • Page 32: Watchdog Flag (Wdf), Key Return Flag (Krf)

    µ PD754202, 754202(A) 9.2 Watchdog Flag (WDF), Key Return Flag (KRF) The WDF is set by a watchdog timer overflow signal, and the KRF is set by a reset signal generated by the KRn pins. As a result, by checking the contents of WDF and KRF, it is possible to know what kind of reset signal is generated.
  • Page 33 µ PD754202, 754202(A) Figure 9-4. KRF Operation in Generating Each Signal Reset signal Reset signal generation by generation by the KRn input the KRn input STOP instruction External RESET STOP instruction KRF clear instruction execution signal generation execution execution External RESET STOP HALT Operation...
  • Page 34: Mask Option

    µ PD754202, 754202(A) 10. MASK OPTION The µ PD754202 has the following mask options: • Mask option of P70/KR4 through P73/KR7 Pull-up resistors can be connected to these pins. (1) No pull-up resistor connection (2) Connection of a 30-kΩ (typ.) pull-up resistor in 1-bit units. (3) Connection of a 100-kΩ...
  • Page 35: Instruction Sets

    µ PD754202, 754202(A) INSTRUCTION SETS (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to “RA75X ASSEMBLER PACKAGE USERS’...
  • Page 36 µ PD754202, 754202(A) (2) Legend in explanation of operation : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : XA register pair; 8-bit accumulator : BC register pair : DE register pair : HL register pair...
  • Page 37 µ PD754202, 754202(A) (3) Explanation of symbols under addressing area column MB = MBE•MBS (MBS = 0, 15) MB = 0 MBE = 0 : MB = 0 (000H-07FH) MB = 15 (F80H-FFFH) Data memory addressing MBE = 1 : MB = MBS (MBS = 0, 15) MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH addr = 0000H-07FFH...
  • Page 38 µ PD754202, 754202(A) Number Instruction Number Addressing Mnemonic Operand of machine Operation Skip condition group of bytes area cycles A ← n4 Transfer A, #n4 String effect A instruction reg1 ← n4 reg1, #n4 XA ← n8 XA, #n8 String effect A HL ←...
  • Page 39 µ PD754202, 754202(A) Number Instruction Number Addressing Mnemonic Operand of machine Operation Skip condition group of bytes area cycles CY ← (fmem.bit) Bit transfer MOV1 CY, fmem.bit instructions CY ← (pmem CY, pmem.@L .bit(L 7–2 3–2 1–0 CY ← (H+mem CY, @H+mem.bit .bit) 3–0...
  • Page 40 µ PD754202, 754202(A) Number Instruction Number Addressing Mnemonic Operand of machine Operation Skip condition group of bytes area cycles reg ← reg+1 Increment INCS reg = 0 rp1 ← rp1+1 Decrement rp1 = 00H instructions (HL) ← (HL)+1 (HL) = 0 (mem) ←...
  • Page 41 µ PD754202, 754202(A) Number Instruction Number Addressing Mnemonic Operand of machine Operation Skip condition group of bytes area cycles Memory bit SKTCLR fmem.bit Skip if (fmem.bit) = 1 and clear (fmem.bit) = 1 manipulation instructions pmem.@L Skip if (pmem .bit(L )) = 1 and clear (pmem.@L) = 1 7–2...
  • Page 42 µ PD754202, 754202(A) Number Instruction Number Addressing Mnemonic Operand of machine Operation Skip condition group of bytes area cycles (SP–2) ← ×, ×, MBE, RBE Subroutine CALLA Note !addr1 (SP–6) (SP–3) (SP–4) ← 0, PC stack control 10–0 (SP–5) ← 0, 0, 0, 0 instructions ←...
  • Page 43 µ PD754202, 754202(A) Number Instruction Number Addressing Mnemonic Operand of machine Operation Skip condition group of bytes area cycles IME (IPS.3) ← 1 Interrupt control IE××× ← 1 instructions IE××× IME (IPS.3) ← 0 IE××× ← 0 IE××× A ← PORTn Note 1 Input/output A, PORTn...
  • Page 44: Electrical Specifications

    µ PD754202, 754202(A) ELECTRICAL SPECIFICATIONS ° Absolute Maximum Ratings (T = 25 Parameter Symbol Test Conditions Ratings Unit Supply voltage –0.3 to +7.0 Input voltage –0.3 to V + 0.3 Output voltage –0.3 to V + 0.3 Output current, high Per pin Pins except P32 –10...
  • Page 45 µ PD754202, 754202(A) ° System Clock Oscillator Characteristics (T = –40 to +85 C, V = 1.8 to 6.0 V) Resonator Recommended Constant Parameter Testing Conditions MIN. TYP. MAX. Unit Note 2 Ceramic Oscillation Note 1 resonator frequency (f Oscillation After V reaches MIN.
  • Page 46 µ PD754202, 754202(A) RECOMMENDED CIRCUIT CONSTANTS Ceramic Resonator (T = –20 to +80 ˚C) Oscillation voltage Circuit constant (pF) Frequency range (V Manufacturer Product Remark (MHz) MIN.(V) MAX.(V) Murata Mfg. CSB1000J Note Rd = 2.2 kΩ Co., Ltd. CSA2.00MG040 – CST2.00MG040 –...
  • Page 47 µ PD754202, 754202(A) DC Characteristics (T = –40 to +85 ˚C, V = 1.8 to 6.0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit High-level output current Per pin Pins except P32 –5 Only P32, –7 –15 = 3.0 V, –2.0 V All pins total –20...
  • Page 48 µ PD754202, 754202(A) ° DC Characteristics (T = –40 to +85 C, V = 1.8 to 6.0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit = 5.0 V ± 10 % Supply current Note 1 4.19 MHz Note 2 = 3.0 V ±...
  • Page 49 µ PD754202, 754202(A) ° AC Characteristics (T = –40 to +85 C, V = 1.8 to 6.0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit CPU clock cycle time Note 1 When system µ s 2.7 V ≤ V ≤...
  • Page 50 µ PD754202, 754202(A) AC Timing Test Points (Excluding X1 Input) (MIN.) (MIN.) (MAX.) (MAX.) (MIN.) (MIN.) (MAX.) (MAX.) Clock Timing X1 input – 0.1 V 0.1 V Interrupt Input Timing INTL INTH INT0, KR4-7 RESET Input Timing RESET...
  • Page 51 µ PD754202, 754202(A) ° Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (T = –40 to +85 Parameter Symbol Test Conditions MIN. TYP. MAX. Unit µ s Release signal set time t SREL Oscillation stabilization Release by RESET Note 2 WAIT Note 1 wait time...
  • Page 52 µ PD754202, 754202(A) Data Retention Timing (Standby release signal: on releasing STOP mode by interrupt signal) HALT mode STOP mode Operation mode Data retention mode SREL Execution of STOP instruction Standby release signal (interrupt request) WAIT...
  • Page 53: Characteristic Curves (Reference Values)

    µ PD754202, 754202(A) CHARACTERISTIC CURVES (REFERENCE VALUES) vs V (System clock: 6.0-MHz crystal resonator) = 25 °C) PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 System clock HALT mode 0.05 0.01 0.005 Crystal resonator 6.0 MHz 22 pF 22 pF 0.001...
  • Page 54 µ PD754202, 754202(A) vs V (System clock: 4.19-MHz crystal resonator) = 25 °C) PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 System clock HALT mode 0.05 0.01 0.005 Crystal resonator 4.19 MHz 22 pF 22 pF 0.001 Supply Voltage V...
  • Page 55: Package Drawings

    µ PD754202, 754202(A) 14. PACKAGE DRAWINGS 20 PIN PLASTIC SOP (300 mil) detail of lead end NOTE ITEM MILLIMETERS INCHES Each lead centerline is located within 0.12 mm (0.005 inch) of 13.00 MAX. 0.512 MAX. its true position (T.P.) at maximum material condition. 0.78 MAX.
  • Page 56 µ PD754202, 754202(A) 20 PIN PLASTIC SHRINK SOP (300 mil) detail of lead end P20GM-65-300B-2 NOTE ITEM MILLIMETERS INCHES Each lead centerline is located within 0.12 7.00 MAX. 0.276 MAX. mm (0.005 inch) of its true position (T.P.) at maximum material condition. 0.575 MAX.
  • Page 57: Recommended Soldering Conditions

    For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions µ...
  • Page 58 µ PD754202, 754202(A) µ PD754202, 75F4264 FUNCTION LIST APPENDIX A. µ PD754202 µ PD75F4264 Note Item Program memory Mask ROM Flash memory 0000H-07FFH 0000H-0FFFH (2048 × 8 bits) (4096 × 8 bits) 000H-07FH (128 × 4 bits) Data memory Static RAM 400H-43FH (32 ×...
  • Page 59: Appendix B. Development Tools

    µ PD754202, 754202(A) APPENDIX B. DEVELOPMENT TOOLS The following development tools are provided for system development using the µ PD754202. In the 75XL Series, the relocatable assembler which is common to the series is used in combination with the device file of each product. Language processor RA75X relocatable assembler Part number...
  • Page 60 µ PD754202, 754202(A) Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the µ PD754202. The system configurations are described as follows. Note 1 Hardware IE-75000-R In-circuit emulator for debugging the hardware and software when developing applica- tion systems that use the 75X Series and 75XL Series.
  • Page 61 µ PD754202, 754202(A) OS for IBM PC The following IBM PC OS’s are supported. Version PC DOS Ver. 5.02 to Ver. 6.3 J6.1/V Note to J6.3/V Note MS-DOS Ver. 5.0 to Ver. 6.22 Note Note 5.0/V to J6.2/V Note IBM DOS J5.02/V Note Only English mode is supported.
  • Page 62: Appendix C. Related Documents

    Document Number Document Name Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 – Guide to Quality Assurance for Semiconductor Devices...
  • Page 63 µ PD754202, 754202(A) [MEMO]...
  • Page 64 µ PD754202, 754202(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
  • Page 65 Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
  • Page 66 The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

This manual is also suitable for:

Mu754202Mu754202a

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