Table of Contents
Advertisement
(b) Release by RESET input
When the RESET signal is input, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 19-4. HALT Mode Release by RESET Input (1/2)
(1) When high-speed system clock is used as CPU clock
RESET signal
Status of CPU
Operating mode
(High-speed
system clock)
High-speed
system clock
RESET signal
Operating mode
Status of CPU
(Ring-OSC clock)
Ring-OSC clock
Remarks 1. f
: High-speed system clock oscillation frequency
XP
2. f
: Ring-OSC clock oscillation frequency
R
CHAPTER 19 STANDBY FUNCTION
HALT
instruction
HALT mode
Oscillates
(2) When Ring-OSC clock is used as CPU clock
HALT
instruction
HALT mode
Oscillates
User's Manual U16899EJ2V0UD
Operation
Reset
period
stopped
Operating mode
(17/f
)
(Ring-OSC clock)
R
Oscillation
Oscillates
stopped
Oscillation stabilization time
11
16
(2
/f
to 2
/f
)
XP
XP
Reset
Operation
Operating mode
period
stopped
(17/f
)
(Ring-OSC clock)
R
Oscillation
Oscillates
stopped
383
Advertisement
Table of Contents
