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9.4.4
The watchdog timer stops counting during HALT instruction execution regardless of whether the operation clock of
the watchdog timer is the clock to peripheral hardware (f
released, counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0 but holds its value.
CPU operation
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Watchdog timer
Watchdog timer operation in HALT mode (when "low-speed Ring-OSC can be stopped by software" is
selected by option byte)
Normal operation
f
CPU
f
or f
XP
RL
Operating
Operation stopped
CHAPTER 9 WATCHDOG TIMER
) or low-speed Ring-OSC clock (f
XP
Figure 9-8. Operation in HALT Mode
HALT
Preliminary User's Manual U16898EJ1V0UD
). After HALT mode is
RL
Normal operation
Operating
151