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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2
Interrupt Acknowledge Registers
Offset
Bit
3
1
Name
Operation
Reset
2-84
There is one Task Priority Register per processor. Priority levels from 0
(lowest) to 15 (highest) are supported. Setting the Task Priority Register to
15 masks all interrupts to this processor. Hardware will set the task register
to $F when it is reset or when the Init bit associated with this processor is
written to a one.
3
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
R
$00
On PowerPC-based systems, Interrupt Acknowledge is implemented as a
read request to a memory-mapped Interrupt Acknowledge register.
Reading the Interrupt Acknowledge register returns the interrupt vector
corresponding to the highest priority pending interrupt. Reading this
register also has the following side effects.
The associated bit in the Interrupt Pending Register is cleared.
J
Reading this register will update the In-Service register.
J
Reading this register without a pending interrupt will return a value of $FF
hex.
Processor 0 $200A0
Processor 1 $210A0
2
2
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
R
$00
$00
Computer Group Literature Center Web Site
1
1
1
2
1
0 9 8 7 6 5 4 3 2 1 0
VECTOR
R
R
$FF
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