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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2
MPIC Registers
RavenMPIC Registers
3
3
2
2
2
1
0
9
8
7
2-68
There is a possibility for a priority tie between the two processors when
resolving external interrupts. In that case the interrupt is always delivered
to processor 0. This case is not defined in the above rule set.
The following conventions are used in the Raven register charts:
R
Read Only field.
J
R/W
Read/Write field.
J
S
Writing a ONE to this field sets this field.
J
C
Writing a ONE to this field clears this field.
J
The RavenMPIC register map is shown in the following table. The Off
field is the address offset from the base address of the RavenMPIC
registers in the MPC-IO or MPC-Memory space. Note that this map does
not depict linear addressing. The Raven PCI-SLAVE has two decoders for
generating the RavenMPIC select. These decoders will generate a select
and acknowledge all accesses which are in a reserved 256K byte range. If
the index into that 256KB block does not decode a valid RavenMPIC
register address, the logic will return $00000000.
The registers are 8, 16, or 32 bits accessible.
Table 2-9. RavenMPIC Register Map
2
2
2
2
2
2
2
1
1
6
5
4
3
2
1
0
9
8
FEATURE REPORTING REGISTER 0
GLOBAL CONFIGURATION REGISTER 0
MPIC VENDOR IDENTIFICATION REGISTER
PROCESSOR INIT REGISTER
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0 9 8 7 6 5 4 3 2 1 0
Computer Group Literature Center Web Site
Off
$01000
$01020
$01080
$01090
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