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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
PCI Command/ Status Registers
2
Offset
Bit
3
1
Name
Operation
Reset
2-50
3
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
PSTAT
IOSP
IO Space Enable. If set, the Raven will respond to PCI
I/O accesses when appropriate. If cleared, the Raven will
not respond to PCI I/O space accesses.
MEMSP
Memory Space Enable. If set, the Raven will respond to
PCI memory space accesses when appropriate. If cleared,
the Raven will not respond to PCI memory space
accesses.
MSTR
Bus Master Enable. If set, the Raven may act as a master
on PCI. If cleared, the Raven may not act as a PCI master.
PERR
Parity Error Response. If set, the Raven will check
parity on all PCI transfers. If cleared, the Raven will
ignore any parity errors that it detects and continue normal
operation.
SERR
System Error Enable. This bit enables the SERR* output
pin. If clear, the Raven will never drive SERR*. If set, the
Raven will drive SERR* active when a system error is
detected.
FAST
Fast Back-to-Back Capable. This bit indicates that the
Raven is capable of accepting fast back-to-back
transactions with different targets.
$04
2
2
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
Computer Group Literature Center Web Site
1
1
1
2
1
0 9 8 7 6 5 4 3 2 1 0
PCOMM
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