Table of Contents
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data path mapping
data paths
3-62
data transfers
default PCI memory map
default processor memory map
derc
3-40
Disable Error Correction control bit
DMA controller
DRAM addressing
DRAM arbitration
DRAM attributes register
DRAM Base Register
DRAM connection diagram
DRAM enable bits
DRAM size control bits
DRAM speed control bits
DRAM speeds
DRAM tester
DRAM tester control registers
DRAM Tester control registers and Test
SRAM
dynamically changing I/O interrupt configu-
ration
E
ECC
3-13
ECC codes
3-59
ECC Control Register
elog
3-43
embt
3-43
endian conversion
endian issues
End-of-Interrupt Registers
EOI Register
error correction
I
Error Correction Codes
N
error detection
error handling
D
Error Logger Register
E
error logging
X
error notification and handling
error reporting
IN-2
3-64
3-12
1-14
1-9
3-40
4-7
3-59
3-21
3-34
3-36
3-5
3-35
3-35
3-33
3-7
3-15
3-52
3-52
2-87
3-38
2-25
5-11
2-85
2-88
3-13
3-60
3-13
2-28
3-42
3-15
5-10
3-14
ERROR_ADDRESS
3-44
ERROR_SYNDROME
3-43
esbt
3-43
escb
3-43
esen
3-43
example 1
4-15
example 2
4-17
example 3
4-19
examples
4-15
exceptions
5-8
external interrupt service
External Register Set
3-54
external register set
3-21
external register set reads and writes
External Source Destination Registers
External Source Vector/Priority Registers
2-79
F
Falcon ECC memory controller chip set
Falcon internal data paths (simplified)
Falcon pair used with DRAM in a system
Falcon-controlled system registers
fast refresh control bit
3-33
Feature Reporting Register
features 2-1,
3-1
Flash (See ROM/Flash)
four-beat reads/writes
3-6
functional description 1-7, 2-4, 3-6,
G
General Control Register
General Control-Status/Feature Registers
2-33
general information
4-1
General Purpose Registers
generating PCI configuration cycles
generating PCI cycles
2-20
generating PCI interrupt acknowledge cycles
2-25
generating PCI memory and I/O cycles
generating PCI special cycles
Computer Group Literature Center Web Site
Index
2-85
3-22
2-81
3-1
3-4
3-3
1-25
2-72
3-15
4-2
3-32
2-47
2-22
2-21
2-24
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