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Falcon ECC Memory Controller Chipset
Functional Description
3
Performance
Four-beat Reads/Writes
3-6
The following sections describe the logical function of the ASIC. The
Falcon is designed to be used as a set of two chips. A pair of Falcons works
with x1 or wider DRAM memory devices to form a memory system for the
PowerPC 60x bus. A pair of Falcons that is connected to implement a
memory control function is referred to in this document as a "Falcon pair".
The Falcon pair is specifically designed to provide maximum performance
for cache line (four-beat) cycles to and from the PowerPC 60x bus at
66 MHz. This is done by providing a two-way interleave between the 64-
bit PowerPC 60x data bus and the 128-bit (144 with check-bits) DRAM
bus. When a PowerPC 60x bus master begins a quad-aligned, four-beat
read to DRAM, the Falcon pair accesses the full 144-bit width of DRAM
at once so that when the DRAM access time is reached, not only is the first
64-bit double-word of data ready to be transferred to the PowerPC 60x bus
master, but so is the next. While the Falcon pair is presenting the first two
double-words to the PowerPC 60x bus, it cycles CAS without cycling RAS
to obtain the next two double-words. The Falcon pair transfers the next two
double-words to the PowerPC 60x bus after 0 or more idle clocks.
The Falcon pair also takes advantage of the fact that PowerPC 60x
processors can do address pipelining. Many times while a data cycle is
finishing, the PowerPC 60x processor begins a new address cycle. The
Falcon pair can begin the next DRAM access earlier when this happens,
thus shortening the access time. Further savings come when the new
address cycle is to an address close enough to the previous one that it falls
within the same row in the DRAM array. When this happens, the Falcon
pair can transfer the data for the next cycle by cycling CAS without cycling
RAS.
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