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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2
2-24
configuration cycle. Raven decodes the Device Number to determine
which of the upper address lines to assert. The decoding of the five-bit
Device Number is show as follows:
Device Number
00000
00001 - 01010
01011
01100
(etc.)
11101
11110
11111
The Bus Number determines which bus is the target for the configuration
read cycle. Raven will always host PCI bus #0. Accesses that are to be
performed on the PCI bus connected to the Raven must have zero
programmed into the Bus Number. If the configuration access is targeted
for another PCI bus, then that bus number should be programmed into the
Bus Number field. The Raven will detect a non-zero field and convert the
transaction to a Type 1 Configuration cycle.
Generating PCI Special Cycles
Raven supports the method stated in PCI Local Bus Specification 2.0 using
Configuration Mechanism #1 to generate special cycles. To prime Raven
for a special cycle, the host processor must write a 32 bit value to the
CONFIG_ADDRESS register. The contents of the write are defined later
in this chapter under the CONFIG_ADDRESS register definition. After
the write to CONFIG_ADDRESS has been accomplished, the next write
to the CONFIG_DATA register causes the Raven to generate a special
cycle on the PCI bus. The write data is driven onto AD[31:0] during the
special cycle's data phase.
Address Bit
AD31
All Zeros
AD11
AD12
(etc.)
AD29
AD30
All Zeros
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