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Board Description and Memory Maps
1
REG
BIT
FIELD
OPER
RESET
1-28
Memory Configuration Register - $FEF80404
M_FREF Block A/B/C/D Fast Refresh. When this bit is set, it
indicates that a DRAM block requires faster refresh rate.
If any of the four blocks requires faster refresh rate then
the ram ref control bit should be set.
M_SPD[0:1]
Memory Speed. This field relays the memory speed
information as follows:
M_SPD[0:1]
0b00
0b01
0b10
0b11
These two bits reflect the combined status of the four
blocks of DRAM. Initialization software uses this
information to program the ram_spd0 and ram_spd1
control bits in the Falcon's Chip Revision Register.
DRAM Speed
70ns
60ns
Reserved
50ns
Computer Group Literature Center Web Site
DRAM Type
Past Page
Fast Page
Reserved
EDO
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