Table of Contents
Advertisement
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2
2-16
The slave will only honor the Linear Incrementing addressing mode. The
slave will perform a disconnect with data if any other mode of addressing
is attempted.
Device Selection:
The PCI slave will always respond valid decoded cycles as a medium
responder.
Target Initiated Termination:
The PCI slave normally strives to complete transactions without issuing
disconnects or retries. One exception is where the slave is performing
configuration cycles. All configuration cycles will be terminated with a
disconnect after one data beat has been transferred. Another exception is
the issue of a disconnect when asked to perform a transaction with byte
enable 'holes'.
Fast Back-to-Back Transactions:
The PCI slave supports both of the fundamental target requirements for
fast back-to-back transactions. The PCI slave meets the first criteria of
being able to successfully track the state of the PCI bus without the
existence of an IDLE state between transactions. The second criteria
associate with signal turn-around timing is met by default since the slave
functions as a medium responder.
Latency:
The PCI slave does not have any hardware mechanisms in place to
guarantee that the initial and subsequent target latency requirements are
met. Typically this is not a problem since the bandwidth of the MPC bus
far exceeds the bandwidth of the PCI bus. The Raven MPC arbiter has been
designed to give the highest priority for it's own transactions which further
reduces PCI bus latency.
Exclusive Access:
The PCI slave has no mechanism to support exclusive access.
Computer Group Literature Center Web Site
Advertisement
Table of Contents
