Dram Base Register - Motorola MVME3600 Series Programmer's Reference Manual

Falcon ECC Memory Controller Chipset
Table 3-11. Block_A/B/C/D Configurations (Continued)
ram a/b/c/d
siz0-2
3
%100
%101
%110
%111

DRAM Base Register

ADDRESS
BIT
NAME
OPERATION
RESET
3-36
Block
Devices Used
SIZE
128MB
18
144
256MB 36
4
1024MB
144
0MB
-
Note that it is important that all of the ram a/b/c/d siz0-2 bits be set to
accurately match the actual size of their corresponding blocks. This
includes clearing them to %000 if their corresponding blocks are not
present. Failure to do so will cause problems with addressing and with
scrub error logging.
RAM A BASE RAM B BASE
READ/WRITE READ/WRITE
0 PL
RAM A/B/C/D BASE These control bits define the base address for
their block's DRAM. RAM A/B/C/D BASE bits 0-7/8-
15/16-23/24-31 correspond to PowerPC 60x address bits
0 - 7. For larger DRAM sizes, the lower significant bits of
A/B/C/D BASE are ignored. This means that the block's
base address will always appear at an even multiple of its
size. Note that bit 0 is MSB.
Technology
- 8Mx8's 64Mb
- 16Mx1's 16Mb
- 16Mx4's 64Mb
- 16Mx36's 64Mb/16Mb
- 64Mx1's 64Mb
- -
$FEF80018
RAM C BASE
READ/WRITE
0 PL
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Comments
SIMM/DIMM
- Reserved
RAM D BASE
READ/WRITE
0 PL 0 PL