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End-of-Interrupt Registers
Offset
Bit
3
3
2
2
1
0
9
8
Name
Operation
R
Reset
$00
EOI
Programming Notes
External Interrupt Service
The following summarizes how an external interrupt is serviced:
1. An external interrupt occurs.
2. The processor state is saved in the machine status save/restore
3. The external interrupt handler calculates the address of the Interrupt
4. The external interrupt handler issues an Interrupt Acknowledge
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Processor 0 $200B0
Processor 1 $210B0
2
2
2
2
2
2
2
2
1
7
6
5
4
3
2
1
0
9
R
$00
END OF INTERRUPT. There is one EOI register per
processor. EOI Code values other than 0 are currently
undefined. Data values written to this register are ignored;
zero is assumed. Writing to this register signals the end of
processing for the highest priority interrupt currently in
service by the associated processor. The write operation
will update the In-Service register by retiring the highest
priority interrupt. Reading this register returns zeros.
registers. A new value is loaded into the Machine State Register
(MSR). The External Interrupt Enable bit in the new MSR (MSRee)
is set to zero. Control is transferred to the O/S external interrupt
handler.
Acknowledge register for this processor (RavenMPIC Base Address
+ 0x200A00 + (processor ID shifted left 12 bits)).
request to read the interrupt vector from the RavenMPIC. If the
Raven Interrupt Controller Implementation
1
1
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0 9 8 7 6 5 4 3 2 1 0
R
$00
EOI
R
W
$0
$0
2-85
2
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