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Table 2-9. RavenMPIC Register Map (Continued)
3
3
2
2
2
2
2
2
2
1
0
9
8
7
6
5
4
3
TIMER FREQUENCY REPORTING REGISTER
TIMER 0 CURRENT COUNT REGISTER
TIMER 0 VECTOR-PRIORITY REGISTER
TIMER 1 CURRENT COUNT REGISTER
TIMER 1VECTOR-PRIORITY REGISTER
TIMER 2 CURRENT COUNT REGISTER
TIMER 2 VECTOR-PRIORITY REGISTER
TIMER 3 CURRENT COUNT REGISTER
TIMER 3 VECTOR-PRIORITY REGISTER
INT. SRC. 0 VECTOR-PRIORITY REGISTER
INT. SRC. 1 VECTOR-PRIORITY REGISTER
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2
2
2
1
1
1
1
1
1
2
1
0
9
8
7
6
5
4
IPI0 VECTOR-PRIORITY REGISTER
IPI1 VECTOR-PRIORITY REGISTER
IPI2 VECTOR-PRIORITY REGISTER
IPI3 VECTOR-PRIORITY REGISTER
TIMER 0 BASE COUNT REGISTER
TIMER 0 DESTINATION REGISTER
TIMER 1 BASE COUNT REGISTER
TIMER 1DESTINATION REGISTER
TIMER 2 BASE COUNT REGISTER
TIMER 2 DESTINATION REGISTER
TIMER 3 BASE COUNT REGISTER
TIMER 3 DESTINATION REGISTER
INT. SRC. 0 DESTINATION REGISTER
INT. SRC. 1 DESTINATION REGISTER
Raven Interrupt Controller Implementation
1
1
1
1
3
2
1
0 9 8 7 6 5 4 3 2 1 0
SP REGISTER
2
Off
$010a0
$010b0
$010c0
$010d0
$010e0
$010f0
$01100
$01110
$01120
$01130
$01140
$01150
$01160
$01170
$01180
$01190
$011a0
$011b0
$011c0
$011d0
$011e0
$011f0
$10000
$10010
$10020
$10030
2-69
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