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Board Description and Memory Maps
1
!
Warning
1-30
cache to write back dirty cache lines out to system
memory and clears all the tag valid bits.
causes the Glance pair to request and hold the MPC bus
until it has completed the flush operation (approximately
4100 clock cycles). This may be an issue if other devices
cannot wait that long to become MPC bus master.
SXC_RST_
System External Cache Reset. When this bit is cleared, it
invalidates all tags and holds the cache in a reset
condition.
hold the chip in a reset condition. The tag invalidate still
works okay though.
SXC_MI_
System External Cache Miss Inhibit. When this bit is
cleared, it prevents line fills on cache misses.
Software should never clear more than one of these bits at the same time.
If more than one is cleared at the same time, the Glance pair behaves
indeterminately.
There is a bug in Glance - It really does not
Computer Group Literature Center Web Site
This operation
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