Programming Model
MPC60 x Master
3
CSR
CSR
Upper FALCON
Lower FALCON
1903 9609
Figure 3-4. Data Path for Reads from the Falcon Internal CSRs
For writes, internal register or test SRAM data written on the upper half of
the data bus goes to the upper Falcon and is automatically copied by
hardware to the lower Falcon. Internal register or test SRAM data written
on the lower half of the data bus does not go to either Falcon in the pair,
but the access is terminated normally with TA_. (See
Figure
3-5.)
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