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Falcon ECC Memory Controller Chipset
PowerPC 60 x Bus Interface
3
Responding to Address Transfers
Completing Data Transfers
Cache Coherency
3-12
The Falcon pair has a PowerPC slave interface only. It has no PowerPC
master interface. The slave interface is the mechanism for all accesses to
DRAM, ROM/Flash, and Falcon registers/SRAM.
When the Falcon pair detects an address transfer that it is to respond to, it
asserts AACK_ immediately if there is no uncompleted PowerPC 60x bus
data transfer in process. If there is one in process, then the Falcon pair
waits and asserts AACK_ coincident with the uncompleted data transfer's
last data beat if the Falcon pair is the slave for the previous data. If it is not,
it holds off AACK_ until the CLOCK after the previous data transfer's last
data beat.
If an address transfer to the Falcon pair will have an associated data
transfer, the Falcon pair begins a read or write cycle to the accessed entity
(DRAM/ROM/Flash/Internal Register) as soon as the entity is free. If the
data transfer will be a read, the Falcon pair begins providing data to the
PowerPC 60x bus as soon as the entity has data ready and the PowerPC 60x
data bus is granted. If the data transfer will be a write, the Falcon pair
begins latching data from the PowerPC data bus as soon as any previously
latched data is no longer needed and the PowerPC 60x data bus has been
granted.
The Falcon pair supports cache coherency by monitoring the ARTRY_
control signal on the PowerPC 60x bus and behaving appropriately when
it is asserted. When ARTRY_ is asserted, if the access is a read, the Falcon
pair does not source the data for that access. If the access is a write, the
Falcon does not write the data for that access to the DRAM array.
Depending upon when the retry occurs however, the Falcon pair may cycle
the DRAM even though the data transfer does not happen.
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