Hitachi H8/3637 Hardware Manual page 174

upper 8 bits and OCRFL as the lower 8 bits of the register, or OCRFH and OCRFL can be used as
independent 8-bit registers.
OCRFH and OCRFL can be read and written by the CPU, but in 16-bit mode, data transfer with
the CPU takes place via a temporary register (TEMP). For details see 9.3.3, Interface with the
CPU.
Upon reset, OCRFH and OCRFL are each initialized to H'FF.
16-Bit Mode (OCRF): 16-bit mode is selected by clearing bit CKSH2 to 0 in timer control
register F (TCRF). The OCRF contents are always compared with the 16-bit timer counter (TCF).
When the contents match, the compare match flag (CMFH) in TCSRF is set to 1. Also, IRRTFH
in interrupt request register 2 (IRR2) is set to 1. If bit IENTFH in interrupt enable register 2
(IENR2) is set to 1, a CPU interrupt is requested.
Output for pin TMOFH can be toggled by compare match. The output level can also be set to high
or low by bit TOLH of timer control register F (TCRF).
8-Bit Mode (OCRFH, OCRFL): Setting bit CKSH2 in TCRF to 1 results in two 8-bit
independent registers, OCRFH and OCRFL.
The OCRFH contents are always compared with TCFH, and the OCRFL contents are always
compared with TCFL. When the contents match, the compare match flag (CMFH or CMFL) in
TCSRF is set to 1. Also, bit IRRTFH (IRRTFL) in interrupt request register 2 (IRR2) set to 1. If
bit IENTFH (IENTFL) in interrupt enable register 2 (IENR2) is set to 1 at this time, a CPU
interrupt is requested.
The output at pin TMOFH (TMOFL) can be toggled by compare match. The output level can also
be set to high or low by bit TOLH (TOLL) of the timer control register (TCRF).
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