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TMG—Timer mode register G
Bit
OVFH
Initial value
Read/Write
R/(W)
Counter clear
0
1 0
Input capture interrupt edge select
0 Interrupts are requested at the rising edge of the input capture signal
1 Interrupts are requested at the falling edge of the input capture signal
Timer overflow interrupt enable
0 TCG overflow interrupt disabled
1 TCG overflow interrupt enabled
Timer overflow flag L
0 [Clearing condition]
After reading OVFL = 1, cleared by writing 0 to OVFL
1 [Setting condition]
When the value of TCG overflows from H'FF to H'00
Timer overflow flag H
0 [Clearing condition]
After reading OVFH = 1, cleared by writing 0 to OVFH
1 [Setting condition]
When the value of TCG overflows from H'FF to H'00
Note:
Only a write of 0 for flag clearing is possible.
*
7
6
OVFL
OVIE
0
0
R/(W)
R/W
*
*
0
TCG is not cleared
1
TCG is cleared at the falling edge of the input capture signal
TCG is cleared at the rising edge of the input capture signal
1
TCG is cleared at both edges of the input capture signal
5
4
3
IIEGS
CCLR1
0
0
0
R/W
R/W
H'BC
2
1
CCLR0
CKS1
0
0
R/W
R/W
Clock select
0
0
Internal clock:
1
Internal clock:
1 0
Internal clock:
1
Internal clock:
Timer G
0
CKS0
0
R/W
ø/64
ø/32
ø/2
ø /2
W
357
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