Programming And Verification - Hitachi H8/3637 Hardware Manual

6.3.1

Programming and Verification

An efficient, high-speed, high-reliability programming procedure can be used to program and
verify data. This procedure programs the chip quickly without subjecting it to voltage stress and
without sacrificing data reliability. Data in unused address areas is H'FF. Figure 6.4 shows the
basic high-speed, high-reliability programming flow chart.
No
Fail
Figure 6.4 High-Speed, High-Reliability Programming Flow Chart
110
Set program/verify mode
= 6.0 V ± 0.25 V, V
V
CC
Yes
<
n 25
Program with t
No
Overprogram with t
= 5.0 V ± 0.25 V, V
V
CC
No
Start
= 12.5 V ± 0.3 V
PP
Address = 0
n = 0
→
n + 1 n
= 0.2 ms ±5%
PW
Verification OK?
Yes
= 0.2n ms
OPW
Last address?
Yes
Set read mode
= V
PP CC
All addresses
read?
Yes
End
→
Address + 1 address
No