Hitachi H8/3637 Hardware Manual page 33

Table 2.2 Effective Address Calculation
Addressing Mode and
No. Instruction Format
1
Register direct, Rn
15 8 7
op
2 Register indirect, @Rn
15
op
3 Register indirect with
displacement, @(d:16, Rn)
15
op
disp
4
Register indirect with
post-increment, @Rn+
15
op
Register indirect with
pre-decrement, @–Rn
15
op
Effective Address
Calculation Method
4 3 0
rm rn
15
7 6 4 3 0
rm
15
7 6 4 3 0
rm
15
7 6 4 3 0
rm
15
7 6 4 3 0
Incremented or
rm
decremented by 1 if
operand is byte size,
and by 2 if word size
Contents (16 bits) of
register indicated by rm
Contents (16 bits) of
register indicated by rm
disp
Contents (16 bits) of
register indicated by rm
1 or 2
Contents (16 bits) of
register indicated by rm
1 or 2
Effective Address (EA)
3 0
rm
Operand is contents of
registers indicated by rm/rn
0
15
0
15
0 15
0
15
3 0
rn
0
0
0
0
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