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Timer Load Register Y (TLY)
Timer Load Register YH (TLYH)
Timer Load Register YL (TLYL)
Bit
15
14
Initial value
0
Read/Write
W
W
Timer load register Y (TLY) is a 16-bit write-only register that is set with the TCY load
value.
When the load value is set in TLY, that value is simultaneously loaded into TCY, and TCY
starts counting up from that value. In auto-reload operation, the TLY value is loaded into
TCY when TCY overflows. The overflow period can therefore be set in the range of 1 to
65,536 input clock cycles.
TLY is allocated to the same address as TCY.
Upon reset, TLY is initialized to H'0000.
9.5.3
Interface with the CPU
TCY and TLY are 16-bit registers, whereas the data bus between the CPU and on-chip
peripheral modules has an 8-bit width. For this reason, when the CPU accesses TCY or TLY,
it makes use of an 8-bit temporary register (TEMP).
An access must be performed as a 16-bit unit (using two consecutive byte-size MOV
instructions), accessing the upper byte first, then the lower byte. Data will not be transferred
properly if only the upper or only the lower byte is accessed.
Write Access: When the upper byte is written, the upper-byte data is loaded into the TEMP
register. Next when the lower byte is written, the data in TEMP goes to the upper byte of the
register, and the lower-byte data goes directly to the lower byte of the register. Figure 9.16
shows a TLY write operations when H'AA55 is written to TLY.
200
13
12
11
0
0
0
0
W
W
W
TLYH
TLY
10
9
8
7
0
0
0
0
W
W
W
W
6
5
4
3
0
0
0
0
W
W
W
W
TLYL
2
1
0
0
0
0
W
W
W
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