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Interrupt Enable Register 2 (IENR2)
Bit
IENDT
Initial value
Read/Write
R/W
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7—Direct Transfer Interrupt Enable (IENDT): Bit 7 enables or disables direct transfer
interrupt requests.
Bit 7: IENDT
0
1
Bit 6—A/D Converter Interrupt Enable (IENAD): Bit 6 enables or disables A/D converter end
interrupt requests.
Bit 6: IENAD
0
1
Bit 5—Reserved Bit: Bit 5 is reserved: it is always read as 0, and should be used cleared to 0.
Bit 4—Timer G Interrupt Enable (IENTG): Bit 4 enables or disables timer G input capture and
overflow interrupt requests.
Bit 4: IENTG
0
1
Bit 3—Timer FH Interrupt Enable (IENTFH): Bit 3 enables or disables timer FH compare
match and overflow interrupt requests.
Bit 3: IENTFH
0
1
64
7
6
IENAD
—
0
0
R/W
—
Description
Disables direct transfer interrupt requests
Enables direct transfer interrupt requests
Description
Disables A/D converter interrupt requests
Enables A/D converter interrupt requests
Description
Disables timer G interrupts
Enables timer G interrupts
Description
Disables timer FH interrupts
Enables timer FH interrupts
5
4
IENTG
IENTFH
0
0
R/W
R/W
3
2
IENTFL
IENTY
0
0
R/W
R/W
1
0
—
0
1
—
(initial value)
(initial value)
(initial value)
(initial value)
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