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Bit 0: WRST
0
1
Timer Counter W (TCW)
Bit
TCW7
Initial value
Read/Write
R/W
Timer counter W (TCW) is an 8-bit read/write up-counter that is incremented by an input
internal clock. The input clock is ø/8192. The TCW value can be read or written by the CPU
at any time.
When TCW overflows (from H'FF to H'00), an internal reset signal is generated and WRST in
TCSRW is set to 1. Upon reset, TCW is initialized to H'00.
9.6.3
Operation
The watchdog timer is provided with an 8-bit timer that increments with each input clock
(ø/8192). If 1 is written to WDON while writing 0 to B2WI when TCSRWE in TCSRW is set
to 1, TCW begins counting up. When a clock pulse is input after the TCW count value has
reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The
internal reset signal is output for a period of 512 ø
and when a value is set in TCW, the count-up starts from that value. An overflow period in
the range of 1 to 256 input clock cycles can therefore be set, according to the TCW value.
Figure 9.19 shows an example of watchdog timer operation.
208
Description
[Clearing conditions]
•
Reset by RES pin
•
When 0 is written to WRST while writing 0 to B0WI when TCSRWE is set
to 1
[Setting condition]
When TCW overflows and an internal reset signal is generated
7
6
TCW6
TCW5
0
0
R/W
R/W
5
4
TCW4
TCW3
0
0
R/W
R/W
clock cycles. TCW is a writable counter,
osc
3
2
TCW2
TCW1
0
0
R/W
R/W
(initial value)
1
0
TCW0
0
0
R/W
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