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Break Detection and Processing: Break signals can be detected by reading the RXD pin directly
when a framing error (FER) is detected. In the break state the input from the RXD pin consists of
all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state SCI3
continues to receive, so if the FER bit is cleared to 0 it will be set to 1 again.
Sending a Mark or Break Signal: When the TXD bit in PMR6 is cleared to 0, the TXD pin
becomes an I/O port, the level and direction (input or output) of which are determined by the
PDR and PCR bits. This feature can be used to place the TXD pin in the mark state or to send
a break signal.
To place the serial communication line in the mark (1) state before TE is set to 1, set the PDR
and PCR bits both to 1. The TXD pin becomes an I/O port outputting the value 1.
To send a break signal during transmission, set the PCR bit to 1 and clear the PDR bit to 0,
then clear the TXD bit in PMR6 to 0.
When the TXD bit in PMR6 is cleared to 0, the TXD pin becomes an I/O port outputting 0,
regardless of the current transmission status.
Receive Error Flags and Transmit Operation (Sysnchronous Mode Only): When a receive
error flag (ORER, PER, or FER) is set to 1, SCI3 will not start transmitting even if TDRE is
cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that
clearing RE to 0 does not clear the receive error flags.
Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous
mode SCI3 operates on a base clock with 16 times the bit rate frequency. In receiving, SCI3
synchronizes internally with the falling edge of the start bit, which it samples on the base clock.
Receive data is latched at the rising edge of the eighth base clock pulse. See figure 10.24.
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