Appendix C I/O Port Block Diagrams
C.1
Port 1 Block Diagrams
V
CC
V
CC
P1
7
V
SS
PDR1:
Port data register 1
PCR1:
Port control register 1
PMR1:
Port mode register 1
PUCR1:
Port pull-up control register 1
SBY (low level during reset
and in standby mode)
Figure C.1 (a) Port 1 Block Diagram (Pin P1
Internal
data bus
PUCR1
7
PMR1
7
PDR1
7
PCR1
7
)
7
Timer F module
TMIF
IRQ
3
375