Hitachi H8/3637 Hardware Manual page 265

Transmitting
processor
Receiving
processor A
(ID = 01)
Serial data
MPB: Multiprocessor bit
Figure 10.19 Example of Interprocessor Communication Using Multiprocessor Format
Four communication formats are available. Parity-bit settings are ignored when a multiprocessor
format is selected. For details see table 10.14.
For a description of the clock used in multiprocessor communication, see 10.3.4, Operation in
Asynchronous Mode.
Communication line
Receiving
processor B
(ID = 02)
H'01
(MPB = 1)
ID-sending cycle
(receiving processor
address)
(Data H'AA Sent to Receiving Processor A)
Receiving
processor C
(ID = 03)
H'AA
(MPB = 0)
Data-sending cycle
(data sent to receiving
processor designated
by ID)
Receiving
processor D
(ID = 04)
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