Table of Contents
Advertisement
SCI3 operates as follows when receiving serial data in synchronous mode.
In synchronization with the input or output of the serial clock, SCI3 initializes internally and starts
receiving. Received data is set in RSR from LSB to MSB.
After data has been received, SCI3 checks to confirm that the value of bit RDRF is 0 indicating
that received data can be transferred from RSR to RDR. If this check passes, RDRF is set to 1 and
the received data is stored in RDR. At this time, if bit RIE in SCR3 is set to 1, an RXI interrupt is
requested. If an overrun error is detected, OER is set to 1 and RDRF remains set to 1. Then if bit
RIE in SCR3 is set to 1, an ERI interrupt is requested.
For the overrun error detection conditions and receive data processing, see table 10.15.
Note: Data receiving cannot be continued while a receive error flag is set. Before continuing the
receive operation it is necessary to clear the OER, FER, PER, and RDRF flags to 0.
Figure 10.17 shows a typical receive operation in synchronous mode.
Serial
clock
Serial
Bit 7
data
RDRF
OER
SCI3
RXI request RDRF cleared
operation
User
processing
Figure 10.17 Typical Receive Operation in Synchronous Mode
258
Bit 0
Bit 7
1 frame
RXI request
to 0
Read data
from RDR
Bit 0
Bit 1
1 frame
RDR data
not read
(RDRF = 1)
Bit 6
Bit 7
ERI request due
to overrun error
Overrun error
handling
Advertisement
Table of Contents
