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11.2.2
DTMF Load Register (DTLR)
Bit
Initial value
Read/Write
DTLR is an 8-bit read/write register that specifies the ratio by which the clock frequency at the
OSC pins is divided for input to the DTMF generator.
Upon reset, DTLR is initialized to H'E0.
Bits 7 to 5—Reserved Bits: Bits 7 to 5 are reserved: they are always read as 1, and cannot be
modified.
Bits 4 to 0—OSC Clock Division Ratio 4 to 0 (DTL4 to DTL0): Bits 4 to 0 specify a division
ratio of the OSC clock frequency which will generate a 400-kHz clock for input to the DTMF
generator. The ratio is set as a counter value from 3 to 25, corresponding to OSC clock frequencies
of 1.2 to 10 MHz (in 400-kHz steps).
Bit 4:
Bit 3:
Bit 2:
DTL4
DTL3
DTL2
0
0
0
1
:
:
:
1
1
0
1
Note: * Don't care
These bits must be set to the correct value. Normal DTMF signal output frequencies will not be
obtained if these bits are set to a value not matching the clock input at the OSC pins. Operation is
not guaranteed if these bits are set to a value other than 3 to 25.
276
7
6
—
—
—
1
1
—
—
—
Bit 1:
Bit 0:
DTL1
DTL0
0
0
1
1
0
1
0
0
:
:
0
1
1
*
*
*
5
4
DTL4
DTL3
1
0
R/W
R/W
Division Ratio
Illegal setting
Illegal setting
Illegal setting
3
4
:
25
Illegal setting
Illegal setting
3
2
DTL2
DTL1
0
0
R/W
R/W
Description
OSC Clock
Frequency
1.2 MHz
1.6 MHz
:
10 MHz
1
0
DTL0
0
0
R/W
(initial value)
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