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SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
Prior to start of interrupt
exception handling
Legend:
PC
:
Upper 8 bits of program counter (PC)
H
PC
:
Lower 8 bits of program counter (PC)
L
CCR:
Condition code register
SP:
Stack pointer
1.
PC shows the address of the first instruction to be executed upon
Notes:
return from the interrupt handling routine.
2.
Register contents must always be saved and restored by word access,
starting from an even-numbered address.
* Ignored on return from interrupt.
Figure 3.4 Stack State after Completion of Interrupt Exception Handling
Figure 3.5 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.
Stack area
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4
After completion of interrupt
PC and CCR
saved to stack
CCR
CCR*
PC
H
PC
L
exception handling
Even address
73
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